This Quiz article provides multiple choice questions and answers on digital logic design. This is a required course for many electrical engineers and can be a challenging subject. With this resource, you can test your knowledge and keep up with the latest design trends.

Digital Logic Design Multiple Choice Questions with Answers pdf for MCA, BCA, and other IT Academic and Competitive examinations.

#### Brief About Digital logic design

Digital Logic Design is the process of designing and constructing digital circuits. The design can be done in a number of different ways, but all involve calculating voltages and currents and then manipulating these numbers to create a working circuit.

There are many different tools that can be used for this purpose, but the most common ones are schematics software programs and breadboard software.

## Digital Logic Design Multiple Choice Questions with Answers

1. ___ circuits are those whose outputs depend only on the current inputs.

`[expand title="`

**Show Answer**"]Combinational[/expand]

2. CPU stands for ___.

`[expand title="`

**Show Answer**"]Central Processing Unit[/expand]

3. Multiplexers are examples of combinational circuits. (State true or false)

`[expand title="`

**Show Answer**"]True[/expand]

4. A ___ adder is a digital circuit that accepts two inputs and performs addition on them and generates two outputs known as sum(S) and carry(C).

`[expand title="`

**Show Answer**"]Half[/expand]

5. A full adder is a digital circuit that can handle carry input. (State true or false)

`[expand title="`

**Show Answer**"]True[/expand]

6. The ___ is a combinational circuit that is used to perform the subtraction of two bits.

`[expand title="`

**Show Answer**"]Half subtractor[/expand]

7. The ___ is used to perform subtraction of three bits, input A (minuend), input B (subtrahend), and third input called ___ and produces two outputs D (difference) and B (borrow).

`[expand title="`

**Show Answer**"]Full subtractor, Borrow in[/expand]

8. The ___ adder that adds two four-bit numbers is called a 4-bit parallel adder.

`[expand title="`

**Show Answer**"]Parallel[/expand]

9. A parallel binary subtractor that subtracts two n bit binary numbers in parallel is called a full binary subtractor. (State true or false)

`[expand title="`

**Show Answer**"]False[/expand]

10. A ripple carries adder is called so because each carry bit gets rippled into the next stage. (State true or false)

`[expand title="`

**Show Answer**"]False[/expand]

11. One of the most serious drawbacks of this adder is that the delay increases linearly with the ___.

`[expand title="`

**Show Answer**"]Bit length[/expand]

12. ___adders do not wait for the carry to ripple through the circuit.

`[expand title="`

**Show Answer**"]Carry look ahead[/expand]

13. The expression (A + C)(AD + AD) + AC + C can be minimized to ___.

`[expand title="`

**Show Answer**"]A+C[/expand]

14. A ___is a visual representation of a Boolean function.

`[expand title="`

**Show Answer**"]Karnaugh map (K-map)[/expand]

15. In a K map, a group of eight 1’s is called ___.

`[expand title="`

**Show Answer**"]Octet[/expand]

16. Don’t care value may be considered as ___ in case of SOP and ___ in case of POS expressions respectively.

`[expand title="`

**Show Answer**"]1, 0[/expand]

17. The simplified form of the expression using the K-map is ___.

`[expand title="`

**Show Answer**"]F= AB+BC[/expand]

18. A ___ is an implicant of the function that is not included in any other implicant of the function.

`[expand title="`

**Show Answer**"]Prime implicant[/expand]

19. When the number of variables is more than six in a given Boolean expression, Quine–McCluskey (Q-M) method will be used. (State true or false)

`[expand title="`

**Show Answer**"]True[/expand]

20. The implementation of a Boolean function with ___ logic requires that the function be simplified in the sum of product form.

`[expand title="`

**Show Answer**"]NAND-NAND[/expand]

21. The NOR function is a dual of the ___ function.

`[expand title="`

**Show Answer**"]NAND[/expand]

22. In the product of sums form, we implement all sum terms using AND gates. (State true or false)

`[expand title="`

**Show Answer**"]False[/expand]

23. ___ of a number is formed by obtaining 9’s complement of a number and adding 1 to the 9’s complement.

`[expand title="`

**Show Answer**"]10’s[/expand]

24. A ___ bit is an extra bit attached to a binary message to make the total number of 1’s either odd or even.

`[expand title="`

**Show Answer**"]Parity[/expand]

25. ___ gates are useful for generating and checking a parity bit that is used for detecting/correcting errors during the transmission of binary data over communication channels.

`[expand title="`

**Show Answer**"]Exclusive OR[/expand]

26. A multiplexer with 2n data input lines requires ___ number of “control” or select lines to select the input line.

`[expand title="`

**Show Answer**"]n[/expand]

27. A 4: 1 Mux selects one of the input lines and connects it to the output line using 2 select lines. (State true or false)

`[expand title="`

**Show Answer**"]True[/expand]

28. Demultiplexer is also called ___.

`[expand title="`

**Show Answer**"]Data distributor[/expand]

29. ___ accepts an active level (i.e. HIGH) on one of its inputs and converts it into coded output such as binary or BCD.

`[expand title="`

**Show Answer**"]Encoder[/expand]

30. LED stands for ___.

`[expand title="`

**Show Answer**"]Light Emitting Diode[/expand]

31. Which of the following is the BCD-to-7-segment decoder/driver

(a) IC 7446

(b) IC 7464

(c) IC 77446

(d) IC 6446

`[expand title="`

**Show Answer**"](a) IC 7446[/expand]

32. A ___is a combinational logic circuit that compares the magnitude of two binary numbers and determines if one number is greater than, less than, or equal to the other number.

`[expand title="`

**Show Answer**"]Magnitude comparator[/expand]

33. IC 7485 which is a ___bit comparator.

`[expand title="`

**Show Answer**"]4[/expand]

34. BCD adder is a circuit that adds two BCD digits and produces some output digit which is also a BCD. (State true or false)

`[expand title="`

**Show Answer**"]True[/expand]

35. BCD subtractor does the subtraction using either ___ complement method or ___ complement method.

`[expand title="`

**Show Answer**"]9’s, 10’s[/expand]

36. In case SR latch using NOR gates, the ___condition exists when S=R=1.

`[expand title="`

**Show Answer**"]Forbidden[/expand]

37. In the case of ___flip flop input data appears at the output after some time.

`[expand title="`

**Show Answer**"]D[/expand]

38. When J=K=1 and CLK=1, the flip flop toggles as long as the clock signal is HIGH (True or False?).

`[expand title="`

**Show Answer**"]False[/expand]

39. The race around condition exists in ___ flip flop.

`[expand title="`

**Show Answer**"]JK[/expand]

40. T flip flop state toggles when T=1 and CLK=1. (State true or false)

`[expand title="`

**Show Answer**"]True[/expand]

41. When a flip flop responds to the HIGH or LOW level of the clock signal it is called ___ triggering.

`[expand title="`

**Show Answer**"]Level[/expand]

42. When a flip-flop change states either when the clock pulse is changing from LOW to HIGH or from HIGH to LOW, then it is called ___.

`[expand title="`

**Show Answer**"]Edge triggering[/expand]

43. Master-slave flip flop will avoid the ___ condition.

`[expand title="`

**Show Answer**"]Race around[/expand]

44. Preset and Clear inputs are called ___ inputs.

`[expand title="`

**Show Answer**"]Asynchronous[/expand]

45. A ___ circuit is a circuit whose output depends on both the current inputs and the past inputs.

`[expand title="`

**Show Answer**"]Sequential[/expand]

46. Sequential circuit uses the combinational logic circuit, memory, and clock signal for its operation. (True or False?)

`[expand title="`

**Show Answer**"]True[/expand]

47. In ___ sequential circuit an event does not wait for timing pulses.

`[expand title="`

**Show Answer**"]Unclocked[/expand]

48. Any device or circuit that has two stable states is called ___.

`[expand title="`

**Show Answer**"]Bistable[/expand]

49. The term flip-flop is used exclusively for ___ circuits.

`[expand title="`

**Show Answer**"]Clocked[/expand]

50. The ___ is a digital sequential circuit that counts the number of input pulses applied.

`[expand title="`

**Show Answer**"]Counter[/expand]

51. Register is a group of ___.

`[expand title="`

**Show Answer**"]Flip-flops[/expand]

52. ___ is a group of flip-flops combined and connected together to facilitate the movement of data bits from one flip flop to another.

`[expand title="`

**Show Answer**"]Shift Register[/expand]

53. Shift registers are used only for data storage but not for the movement of data. (State true or false)

`[expand title="`

**Show Answer**"]False[/expand]

54. SIPO stands for___.

`[expand title="`

**Show Answer**"]Serial-in to Parallel-out[/expand]

55. In ___ shift register, the data input is given in parallel to the input line of each of the flip-flops, and outputs are read out serially from the single output line (Serial Data Out).

`[expand title="`

**Show Answer**"]Parallel-In, Serial-Out (PISO)[/expand]

56. In the PIPO shift register a single clock pulse is sufficient to store and read the data bits. (State true or false)

`[expand title="`

**Show Answer**"]True[/expand]

57. A shift register that can shift the data in both directions (shift either left or right) is called a ___ shift register.

`[expand title="`

**Show Answer**"]Bi-directional[/expand]

58. A shift register that can shift the data in both directions as well as load it serially and parallelly is known as a ___ shift register.

`[expand title="`

**Show Answer**"]Universal[/expand]

59. The integrated circuit (IC) chip 74LS194 is a universal shift register (State true or false)

`[expand title="`

**Show Answer**"]True[/expand]

60. A shift register that can exhibit a specified sequence of states like that of a counter is known as ___.

`[expand title="`

**Show Answer**"]Shift register counters[/expand]

61. An n-stage Johnson counter yields a count sequence of length 4n. (True or False?).

`[expand title="`

**Show Answer**"]False[/expand]

62. SISO shift register can be used to introduce a time delay. (True or False?)

`[expand title="`

**Show Answer**"]True[/expand]

63. In the case of universal shift register IC 74LS194, shift-right is done synchronously with the positive edge of the clock when S0 is High and S1 is Low. (State true or false)

`[expand title="`

**Show Answer**"]True[/expand]

64. A ___ is a digital circuit that generates a desired sequence of bits in synchronization with a clock.

`[expand title="`

**Show Answer**"]Sequence generator[/expand]

65. In ___ counters a common clock is connected to clock inputs of all the flip flops.

`[expand title="`

**Show Answer**"]Synchronous[/expand]

66. A 3 bit asynchronous up counter counts from ___ in an upward direction.

`[expand title="`

**Show Answer**"]0 to 7[/expand]

67. We can build a faster counter by clocking all flip-flops. (True or False?)

`[expand title="`

**Show Answer**"]True[/expand]

68. When the control input count-up/down=0 in the Up/Down counter, then the counter works as an up counter. (State true or false)

`[expand title="`

**Show Answer**"]False[/expand]

69. In many applications, it is important to decode different states of the counter whose number equals the modulus of the counter. (True or False?)

`[expand title="`

**Show Answer**"]True[/expand]

70. The ___ representation of a sequential circuit consists of three sections labeled present state, next state, and output.

`[expand title="`

**Show Answer**"]State table[/expand]

71. An n-bit binary counter consists of n flip-flops and can count in binary from ___.

`[expand title="`

**Show Answer**"]0 to 2n – 1[/expand]

72. How many flip-flops are required to design a Mod-6 counter?

`[expand title="`

**Show Answer**"]Three(3)[/expand]

73. ___ of a counter is the number of different states that a counter can go through before it comes back to the initial state to repeat the count sequence.

`[expand title="`

**Show Answer**"]Modulus[/expand]

74. When a product of sums form of a logic expression is in canonical form, each sum term is called a ___.

`[expand title="`

**Show Answer**"]Maxterm[/expand]

75. The canonical form of the expression X + XY’ is ___.

`[expand title="`

**Show Answer**"]XY + XY′[/expand]

76. A ___ is an electronic circuit that has one or more inputs but only one output.

`[expand title="`

**Show Answer**"]Logic gate[/expand]

77. Less number of gates means less power consumption. (State true or false)

`[expand title="`

**Show Answer**"]True[/expand]

78. The Boolean expression X+X′Y+Y′+(X+Y′) X′Y after simplification yields ___.

`[expand title="`

**Show Answer**"]1[/expand]

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#### Conclusion:

Digital logic design is an important process in the development of digital systems. It is used to create the basic building blocks of these systems, which are then used to create more complex structures.

By understanding the principles behind the digital logic design, you can develop a deeper understanding of how digital systems work and be better prepared to work with them.

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