Advanced Computer Architecture MCQs with Answers pdf
The definition of Advanced Computer Architecture is a field of study that deals with the design of computers that are faster, more reliable and consume less power. Low Power Design or Green Computing is the branch of computer architecture that deals with these issues.
The term “Advanced Computer Architecture” is used to describe a class of computer systems that are more sophisticated than traditional ones.
They may have features such as parallel processing, multicore processors, and large memory caches. This allows them to handle more complex tasks at higher speeds.
Advanced Computer Architecture MCQs with Answers pdf for MCA, BCA and other IT courses & competitive and academic examinations. Let’s start the session:
Advanced Computer Architecture MCQs
1. Computer architecture is abstracted by its ___.
a. Instruction
b. Instruction set
c. Organization
d. None of the above
Answer: (b)
2. Instruction sets include:
a. Opcode
b. Addressing modes
c. Registers
d. All of the above
Answer: (d)
3. Sequential computer was improved from bit-serial to-
a. Bit-parallel
b. Byte serial
c. Word-parallel
d. None of the above
Answer: (c)
4. Von Newmann architecture is slow due to the ___ execution of instructions in a program.
a. Sequential
b. Parallel
c. Non-execution
d. None of the above
Answer: (a)
5. The term ‘computer architecture’ was coined in-
a. 1972
b. 1978
c. 1964
d. 1968
Answer: (c)
6. ___ levels can be used for describing a computer-
a. 1
b. 2
c. 3
d. 4
Answer: (d)
7. ___ Model is more suitable for special purpose computations.
a. SIMD
b. MISD
c. MIMD
d. Both a and b
Answer: (d)
8. Hazards in pipelines can make it necessary to ___ the pipeline.
a. Stall
b. Stake
c. Storm
d. None of the above
Answer: (a)
9. When a machine is pipelined, the ___ execution of instructions requires pipelining of the functional unit.
a. Overloaded
b. Over rode
c. Overlapped
d. Overcrowded
Answer: (c)
10. The ratio which stays constant as performance and cost are increased by equal factors is called:
a. Performance Ratio
b. Cost Ratio
c. Cost-Performance Ratio
d. All of the above
Answer: (c)
11. The cost-performance ratio is a good indicator of ___ quality for small changes.
a. Relative
b. Absolute
c. Absolute relative
d. All of the above
Answer: (a)
12. The processors in a multiprocessor system communicate with each other through ___.
a. Shared memory
b. The shared variable in a common memory
c. Both a & b
d. None of the above
Answer: (b)
13. Interprocessor communication is done through ___ among nodes-
a. Shared variable
b. Shared memory
c. Message passing
d. None of the above
Answer: (c)
14. Explicit vector instructions were introduced with the appearance of ___.
a. Processors
b. Micro processor
c. Intel processors
d. Vector processors
Answer: (b)
15. An SIMD computer exploits ___ parallelism-
a. Spatial
b. Temporal
c. Both a & b
d. None of the above
Answer: (a)
16. Associate memory can be used to build ___ associative processors.
a. SISD
b. SIMD
c. MISD
d. MIMD
Answer: (b)
17. ___ architecture supports the pipelined flow of vectors operands directly from the memory to pipelines and then back to memory.
a. Memory to memory
b. Register to memory
c. Memory to register
d. Register to register
Answer: (a)
18. ___ Architecture uses vector registers to interface between the memory and functional lines.
a. Memory to memory
b. Register to memory
c. Memory to register
d. Register to register
Answer: (d)
19. There are ___ families of pipelined vector processors.
a. 1
b. 2
c. 3
d. 4
Answer: (b)
20. At the system level the description of the ___ architecture is based on processor level building blocks.
a. Abstract
b. Concrete
c. Encapsulated
d. None of the above
Answer: (b)
21. The ___ architecture of a processor is often referred to as simply the processor’s architecture.
a. Abstract
b. Concrete
c. Encapsulated
d. None of the above
Answer: (a)
22. ___ classification shows the architectural evolution from sequential scalar computers to vector processors and parallel computers.
a. Von-Neumann’s
b. Nyquist’s
c. Flynn’s
d. None of the above
Answer: (c)
23. Pipelining offers an economical way to realize ___ parallelism in digital computers.
a. Spatial
b. Temporal
c. Concurrent
d. None of the above
Answer: (b)
24. The concept of ___ processing in a computer is similar to assembly lines in an industrial plan.
a. Vector
b. Sequential
c. Pipeline
d. None of the above
Answer: (c)
25. ___ are streamed into the pipe and get executed in an over-tapped fashion at the subtask level.
a. Successive tasks
b. Independent tasks
c. Concurrent tasks
d. All of the above
Answer: (a)
26. Weather modelling is ___ numeric computation.
a. Structured
b. Unstructured
c. Highly-structured
d. None of the above
Answer: (c)
27. CPI stands for-
a. Clock cycles per instructions
b. Click per instructions
c. Cycles per inch
d. None of the above
Answer: (a)
28. Pipelining yields a reduction in the ___ per instruction.
a. Fetching Line
b. Executions tine
c. Average execution time
d. None of the above
Answer: (c)
29. Pipelining ___ the clock cycle time.
a. Decreases
b. Increases
c. Stabilizes
d. None of the time
Answer: (a)
30. In the _ ___ pipeline, all tasks have equal processing time in all station facilities.
a. Delay
b. Uniform-delay
c. Non-uniform delay
d. None of the above
Answer: (b)
31. CPU of modern digital computers can generally be partitioned into ___ sections.
a. 1
b. 2
c. 3
d. 4
Answer: (c)
32. Partitions of CPU is-
a. Instructions unit
b. Instruction queue
c. Execution unit
d. All of the above
Answer: (d)
33. ___ is faster storage of copies of programs and data.
a. RAM
b. ROM
c. CACHE
d. Hard disk
Answer: (c)
34. Programs and data reside in the ___, which usually consists of interleaved memory modules.
a. Hard disk
b. Main memory
c. Cache
d. ROM
Answer: (b)
35. ___ are fast registers for holding the intermediate results.
a. Latches
b. J.K
c. RS
d. Master-slave
Answer: (a)
36. The instruction queue is ___ storage area-
a. FIFO
b. LIFO
c. FILO
d. All of the above
Answer: (a)
37. ___ may contain multiple functional pipelines for arithmetic logic functions.
a. Instruction queue
b. Instruction unit
c. Execution unit
d. All of the above
Answer: (c)
38. ___ Hazard in pipelines is caused by resource conflicts.
a. Structural
b. Data
c. Control
d. None of the above
Answer: (a)
39. ___ hazards arise when an instruction depends on the results of previous instruction in a way that is exposed by the overlapping of instructions in the pipeline.
a. Structural
b. Data
c. Control
d. None of the above
Answer: (b)
40. ___ hazards arise from the pipelining of branches and other instructions the change the PC.
a. Structural
b. Data
c. Control
d. None o the above
Answer: (c)
41. Computer has gone through two major stages of development ___ & ___.
a. Mechanical & Electrical
b. Pipelining & Distributed
c. Electrical & Concurrency
d. Pipelining & Mechanical
Answer: (a)
42. The study of Computer architecture involves both ___ organization and ___ requirements.
a. Hardware & Software
b. Register & Addressing Modes
c. Assembly & operation codes
d. Software & CPU
Answer: (a)
43.The term Computer Architecture was coined in ___ by the ‘Chief architects of the ___
a. 1974, 360 System
b. 1965, AT & T
c. 1964, IBM System
d. 1984, ENCI System
Answer: (c)
44. True/False
1. The sequential computer was improved bit-serial to word- parallel operations
2. The von-Neumann architecture is fast due to the sequential execution of instructions in the Program.
a. Only 1
b. Only 2
c. Both 1 & 2
d. None of the above
Answer: (a)
45. The study of architecture covers both ___ and ___.
a. Evolutional, Revolution
b. IBM System, Revolution
c. Instruction-set architecture, Machine implementation organizations
d. Evolutional, IBM System
Answer: (c)
46. ___ Architecture supports the pipelined flow of vector operands directly from the memory to Pipelines and then back to the memory. ___ Architecture uses vector registers to interface between the memory and functional Pipelines.
a. Memory –to-register, Register – to – Register
b. Memory –to-Memory, Register – to – Register
c. Memory –to-Pipelines, Register – to – Memory
d. Memory –to-register, Register – to – Pipelines
Answer: (b)
47. ___ offers an economical way to realize temporal parallelism in ___ computers.
a. Pipelining, Super
b. Pipelining, Digital
c. IBM System, Super
d. Evolutional, Digital
Answer: (b)
48. True/False
1. Pipelining is an implementation technique where multiple instructions are overlapped in execution.
2. A Pipeline is a compiler line.
a. Only 1
b. Only 2
c. Both 1 & 2
d. None of the above
Answer: (a)
49. ___ is faster storage of copies of programs & data, which are ready for execution. The Cache is used to close up the speed gap between the Main memory and the ___.
a. Cache Memory, CPU
b. CPU, Cache Memory
c. Primary Memory, Cache Memory
d. None of these
Answer: (a)
50. There are three classes of Hazards ___, ___ & ___.
a. Structural Hazards, Data Hazards, Control hazards.
b. Pipeline, System hazards, Data hazards
c. Linear, Uniform Linear, Cache
d. Pipeline, Linear, Cache
Answer: (a)
51. ___ Complier must be developed to detect :
The concurrency among vector instructions, can be realized with pipelining.
A ___ compiler would regenerate parallelism lost in the use of sequential languages.
a. Intelligent, Vectorizing
b. Vectorizing, Intelligent
c. Parallel, Pipelined. Cache Memory, data hazards
Answer: (a)
52. A ___ scheduling model is presented for multi-pipeline vector processes.
A long vector task can be partitioned into many ___.
a. Parallel task, Sub vectors.
b. Sub vectors, parallel task
c. Vectors, Pipelining
d. None of these
Answer: (a)
53. The instruction Processing Unit fetches and decodes ___ and ___ instructions.
a. Vector, Sub vector
b. Pipelines, parallel task
c. Scalar, Vector
d. Pipelines, Scalar
Answer: (c)
54. The superscalar issue was first formulated as early as ___. The superscalar processors have to issue multiple instructions per cycle, the first task necessarily is ___.
a. 1970, parallel decoding
b. 1975, Pipelines
c. 1980, CISC processors
d. None of these
Answer: (a)
55. Super scalar instruction issue comprises two major aspects
a. Pipelines, Superscalar
b. Vector, Sub vector
c. Issue Policy, Issue Rate
d. None of these
Answer: (c)
56. Superscalar processors have introduced intricate instruction issue policies, involving advanced techniques such as :
a. Shelving, Register naming, Speculative branch processing
b. Parallel decoding, Register naming, Shelving
c. Design space, Issue Policy, Issue Rate
d. None of these
Answer: (a)
57. A ___ machine with memory – Memory
1. Operations can easily be substituted by the compiler and used as a register – register machine.
2. ___ processors have fewer and simpler instructions than CISC processors.
a. GPR, RISC
b. RISC, GPR
c. CPU, CISC
d. RISC, CPU
Answer: (a)
58. Which specific task is not included in superscalar processing?
a. Parallel decoding
b. Superscalar instruction
c. Parallel instruction
d. Pipelines
Answer: (d)
59. Computer architecture is abstracted by its instruction set, which includes ___, ___, ___ & ___
a. opcode, addressing modes, registers, virtual memory
b. Pipelining, Rectorization, concurrency, opcode
c. Addressing modes, Pipelining, Register, opcode
d. Register, virtual memory, restoration, pipelining
Answer: (a)
60. ___ is a standard technique for removing false date dependencies. ___ & ___ dependencies, among register data.
a. Register naming, WAR, WAW
b. WAR, WAW, shelving
c. Register naming, shelving, WAW
d. None of these
Answer: (a)
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