Embedded systems MCQ Questions Answers pdf

Embedded systems MCQ questions answer pdf – multiple choice questions in embedded systems pdf for preparation IT academic and competitive exams.

Embedded systems MCQ Questions Answers pdf

Top 65 Embedded systems mcq questions answers

1. ___ is the basic building block of software written under an RTOS.
Ans. Task

2. TCB stands for ___.
Ans. Task Control Block

3. When other tasks can run, the kernel can switch control to the user-supplied routine instead of to the idle task. (True or False)
Ans. False

4. When a task is first created and made ready to run, the kernel puts it into the ___.
Ans. ready state

5. ___ occurs when higher priority tasks use all of the CPU execution time and lower priority tasks do not get to run.
Ans. CPU starvation

6. On a single-processor system, only one task can run at a time. (Yes or No)
Ans. Yes

7. What happens when memory is acquired but not released?
Ans. A memory leak occurs

8. Endless-loop tasks do the majority of the work in the application by handling inputs and outputs.
(True or False)
Ans. True

9. Tasks synchronize and communicate amongst themselves by using ___.
Ans. intertask primitives

10. The ___ tracks the number of times a semaphore has been acquired or released by maintaining a token count.
Ans. Kernel

11. The ___ is the part of the scheduler that performs context switching and changes the flow of execution.
Ans. dispatcher

12. When a binary semaphore’s value is 0, the semaphore is considered ___.
Ans. Unavailable

13. Ownership of a mutex is gained when a task first locks the mutex by releasing it. (True or False)
Ans. False

14. What happens when a higher priority task is blocked and is waiting for a resource being used by a lower priority task?
Ans. Priority inversion occurs

15. ___ specify the initial semaphore state and the task-waiting order.
Ans. Binary

16. To clear all tasks waiting on a semaphore task-waiting list, some kernels support a ___ operation.
Ans. Flush

17. Two tasks can communicate for the purpose of synchronization without exchanging data. (True or False)
Ans. True

18. A ___ can be used to serialize access to a shared resource.
Ans. semaphore

19. A message queue is like a ___.
Ans. Pipeline

20. QCB stands for ___.
Ans. Queue Control Block

21. Which scheduling provides each task with an equal share of the CPU execution time?
Ans. Round-robin

22. ___ are concurrent and independent threads of execution that can compete for CPU execution time.
Ans. Tasks

23. Different kernels store message queues in different locations in memory. (True or False)
Ans. True

24. ___ are much like queues.
Ans. Mailboxes

25. ___ are kernel objects that provide unstructured data exchange and facilitate synchronization among tasks.
Ans. Pipes

26. Creating a named pipe is similar to creating a ___.
Ans. File

27. A pipe is mainly used for ___ or ISR-to-task data transfer.
Ans. task-to-task

28. An event register can count the occurrences of the same event while it is pending. (True or False)
Ans. False

29. A ___ is a software interrupt that is generated when an event has occurred.
Ans. Signal

30. The number and type of signals defined is both system-dependent and ___ dependent.
Ans. RTOS

31. A condition variable can be associated with ___.
Ans. multiple conditions

32. A task must first acquire the ___ before evaluating the predicate.
Ans. mutex

33. Embedded systems must be reliable. (True or False)
Ans. True

34. Typically, the processor’s performance is expressed in ___.
Ans. MIPS

35. ___ IO operations are at certain fixed data rates.
Ans. Synchronous

36. ___ are the portions of the program code that handle the interrupt requests.
Ans. Interrupt Service Routines (ISR)

37. The time required for the CPU to return to the interrupted code /highest priority task is called ___.
Ans. interrupt recovery time

38. An embedded system with a single CPU can run only one process at an instance. (True/False)
Ans. True

39. Errors dealing with queues can be reduced by ___.
Ans. Encapsulation

40. In embedded systems code must be stored in ___ and data in ___.
Ans. ROM, RAM

41. ___ is a real-time operating system made and sold by Wind River Systems of Alameda, California, USA.
Ans. VxWorks

42. ___ is based on the idea of running most of the OS in the form of a number of small tasks, known as servers.
Ans. QNX

43. In a multi-tasking RTOS, each task needs to be allocated with an amount of memory for storing their contexts for ___.
Ans. context switching

44. Heap memory is typically used by the kernel for dynamic memory allocation of data space for tasks. (True/False)
Ans. False

45. Fundamental to the operation of most pre-emptive RTOSs is the concept of a tick timer or heartbeat. (True/False)
Ans. True

46. What is the advantage of a short system tick?
Ans. Accurate timings

47. ARM is an acronym for ___.
Ans. Advanced RISC Machines

48. The RISC architecture follows the philosophy that ___ instruction should be performed every clock cycle.
Ans. One

49. ___ is a von Neumann architecture machine, while ___ uses Harvard architecture.
Ans. ARM7, ARM9

50. SHARC is a high-performance floating-point and fixed-point DSP from Analog Devices. (True/False)
Ans. True

51. CAN stands for ___.
Ans. Controller Area Network

52. ___ is generically referred to as a “two-wire interface”.
Ans. I²C

53. The I²C reference design has a ___ address space with 16 reserved addresses.
Ans. 7-bit

54. The transmission starts when SDL is pulled low while SCL remains high. (True or False)
Ans. True

55. The CAN is a ___ type of bus.
Ans. broadcast

56. CAN is a synchronous bus – all transmitters must send at the same time for bus arbitration to work.
(True or False)
Ans. True

57. When all nodes are transmitting 1s, the bus is said to be in the ___ state.
Ans. recessive

58. Using ___ devices, high baud rates and high busloads with many messages can be handled.
Ans. Full CAN

59. ___ protocol provides connectionless, packet-based communication.
Ans. Internet

60. A node that transmits data among different types of networks is known as a ___.
Ans. Router

61. 68. The canonical example of a pipelined processor is a ___ processor, with five stages.
Ans. RISC

62. HTTP stands for ___.
Ans. HyperText Transport Protocol

63. ___ is a little-endian processor.
Ans. SHARC

64. Which is the latest processor in the Tiger SHARC family?
Ans. ADSP-TS201

65. Modern processors have ___ instruction pipelines.
Ans. multi-stage

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